1. Field of the Invention
The present invention relates generally to an epitaxial structure and process thereof for a non-planar transistor, and more specifically to an epitaxial structure and process thereof for a non-planar transistor, which has 4<1,1,1> surfaces.
2. Description of the Prior Art
For decades, chip manufacturers have been making metal-oxide-semiconductor (MOS) transistors faster by making them smaller. As semiconductor processes advance to the very deep sub-micron era such as 65 nm node or beyond, how to increase the driving current for MOS transistors has become a critical issue. In order to improve device performance, crystal strain technology has been developed. Crystal strain technology is becoming more and more attractive as a means for getting better performance in the field of MOS transistor fabrication. Putting a strain on a semiconductor crystal alters the speed at which charges move through that crystal. Strain makes MOS transistors work better by enabling electrical charges, such as electrons, to pass more easily through the silicon lattice of the gate channel. Attempts have been made to use a strained silicon layer, which is grown epitaxially on a silicon substrate with a silicon germanium (SiGe) epitaxial structure or a silicon carbide (SiC) epitaxial structure disposed in between. In this type of MOS transistor, a biaxial compressive or tensile strain occurs in the epitaxy silicon layer due to the silicon germanium or silicon carbide having a larger or smaller lattice constant than silicon; as a result, the band structure alters, and the carrier mobility increases. This enhances the speed performance of the MOS transistors.
With increasing miniaturization of semiconductor devices, various multi-gate MOSFET devices such as fin-field effect transistor devices have been developed. The multi-gate MOSFET is advantageous for the following reasons. Manufacturing processes of multi-gate MOSFET devices can be integrated into traditional logic device processes, and thus are more compatible. In addition, since the three-dimensional structure of the multi-gate MOSFET increases the overlapping area between the gate and the substrate, the channel region is controlled more effectively. This therefore reduces a drain-induced barrier lowering (DIBL) effect and a short channel effect. Moreover, the channel region is longer for the same gate length, which increases the current between the source and the drain.
Due to the above advantages of the epitaxy technology and the multi-gate MOSFET, attempts have been made in the current industry to integrate epitaxy technology with a multi-gate MOSFET to achieve the advantages of both.